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M2020-2021 - VCSO BASED CLOCK PLL

General Description

The M2020/21 is a VCSO (Voltage Controlled SAW Oscillator) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation.

The device is ideal for generating the transmit reference clock for optical network systems supporting 2.5-10 GB data rates.

Key Features

  • Integrated SAW (surface acoustic wave) delay line; low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz or 50kHz to 80MHz).
  • Output frequencies of 15 to 700 MHz.
  • LVPECL clock output (CML and LVDS options available).
  • Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL.
  • Loss of Lock (LOL) output pin.
  • Narrow Bandwidth control input (NBW pin).
  • Hitless Switching (HS) options with or without Phase Build-out (PBO).

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Datasheet Details

Part number M2020-2021
Manufacturer Integrated Circuit Systems
File Size 431.78 KB
Description VCSO BASED CLOCK PLL
Datasheet download datasheet M2020-2021 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Integrated Circuit Systems, Inc. Product Data Sheet M2020/21 VCSO BASED CLOCK PLL GENERAL DESCRIPTION The M2020/21 is a VCSO (Voltage Controlled SAW Oscillator) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for optical network systems supporting 2.5-10 GB data rates. It can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode. The M2020/21 module includes a proprietary SAW (surface acoustic wave) delay line as part of the VCSO. This results in a high frequency, high-Q, low phase noise oscillator that assures low intrinsic output jitter.