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Integrated Circuit Systems

M2020-2021 Datasheet Preview

M2020-2021 Datasheet

VCSO BASED CLOCK PLL

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Integrated
Circuit
Systems, Inc.
Product Data Sheet
M2020/21
VCSO BASED CLOCK PLL
GENERAL DESCRIPTION
The M2020/21 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting 2.5-10 GB data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M2020/21 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
FEATURES
Integrated SAW (surface acoustic wave) delay line;
low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz
or 50kHz to 80MHz)
Output frequencies of 15 to 700 MHz *
LVPECL clock output (CML and LVDS options available)
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin
Narrow Bandwidth control input (NBW pin)
Hitless Switching (HS) options with or without Phase
Build-out (PBO) available for SONET (GR-253) /
SDH (G.813) MTIE and TDEV compliance during
reference clock reselection
Industrial temperature grade available
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
FIN_SEL0
MR_SEL0
MR_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30
31
M2020
32 M 2 0 2 1
16
15
14
33
34 ( T o p V i e w )
13
12
35 11
36 10
P_SEL0
P_SEL1
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M2020-11-622.0800 or M2021-11-622.0800
Input Reference
Clock (MHz)
PLL Ratio
(Pin Selectable)
Output Clock
(MHz)
(M2020)
(M2021)
19.44 or 38.88
(M2020) (M2021)
32 or 16
77.76
155.52
8 622.08
4
622.08
1
Table 1: Example I/O Clock Frequency Combinations
* Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
NBW
LOL
M2020/21
Loop
Filter
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
MR_SEL1:0 2
FIN_SEL1:0 2
P_SEL2:0 3
MUX
0 R Div
(1, 4,
16, 64)
1
Phase
Detector
VCSO
M / R Divider
LUT
M Divider
(1, 4, 16, 64)
Mfin Div
(1, 4, 8, 32) or
( 1, 4, 8, 16)
Mfin Divider
LUT
P Divider
TriState
FOUT0: 1, 4, 8, 32 or TriState
FOUT1: 1, 4, 8 or TriState
P Divider
LUT
FOUT0
nFOUT0
FOUT1
nFOUT1
Figure 2: Simplified Block Diagram
M2020/21 Datasheet Rev 1.0
Revised 30Jul2004
M2020/21 VCSO Based Clock PLL
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400




Integrated Circuit Systems

M2020-2021 Datasheet Preview

M2020-2021 Datasheet

VCSO BASED CLOCK PLL

No Preview Available !

Integrated
Circuit
Systems, Inc.
M2020/21
VCSO BASED CLOCK PLL
Product Data Sheet
PIN DESCRIPTIONS
Number
Name
1, 2, 3, 10, 14, 26 GND
I/O Configuration
Ground
Description
Power supply ground connections.
4
9
5
8
6
7
11, 19, 33
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
Input
Output
Input
Power
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 6.
Power supply connection, connect to +3.3V.
12
13
FOUT1
nFOUT1
Output No internal terminator Clock output pair 1. Differential LVPECL.
15
16
FOUT0
nFOUT0
Output No internal terminator Clock output pair 0. Differential LVPECL.
17
18
25
P_SEL1
P_SEL0
P_SEL2
Input
Internal pull-down resistor1
Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 5,
P Divider Look-Up Table (LUT), on pg. 3.
20
21
nDIF_REF1
DIF_REF1
Input
Biased to Vcc/2 2
Reference clock input pair 1. Differential LVPECL or LVDS.
Internal pull-down resistor1 Resistor bias on inverting terminal supports TTL or LVCMOS.
22
REF_SEL
Input
Internal pull-down resistor1
Reference clock input selection. LVCMOS/LVTTL:
Logic 1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
23
24
nDIF_REF0
DIF_REF0
Input
Biased to Vcc/2 2
Reference clock input pair 0. Differential LVPECL or LVDS.
Internal pull-down resistor 1 Resistor bias on inverting terminal supports TTL or LVCMOS.
27
28
FIN_SEL1
FIN_SEL0
Input
Internal pull-down resistor1
Input clock frequency selection. LVCMOS/LVTTL.
See Table 3, Mfin Divider Look-Up Table (LUT) on pg. 3.
29
30
MR_SEL0
MR_SEL1
Input
Internal pull-down resistor1
M and R divider value selection. LVCMOS/ LVTTL.
See Table 4, M and R Divider Look-Up Table (LUT) on pg. 3.
31 LOL Output
Loss of Lock indicator output. Asserted when internal PLL is
not tracking the input reference for frequency and phase. 3
Logic 1 indicates loss of lock.
Logic 0 indicates locked condition.
32
34, 35, 36
NBW
DNC
Narrow Bandwidth enable. LVCMOS/LVTTL:
Input Internal pull-UP resistor1 Logic 1 - Narrow loop bandwidth, RIN = 2100k.
Logic 0 - Wide bandwidth, RIN = 100k.
Do Not Connect.
Internal nodes. Connection to these pins can cause erratic
device operation.
Note 1: For typical values of internal pull-down and pull-UP resistors, see DC Characteristics on pg. 8.
Table 2: Pin Descriptions
Note 2: Biased toVcc/2, with 50kto Vcc and 50kto ground. See Differential Inputs Biased to VCC/2 on pg. 8.
Note 3: See LVCMOS Output in DC Characteristics on pg. 8.
M2020/21 Datasheet Rev 1.0
2 of 10
Revised 30Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400


Part Number M2020-2021
Description VCSO BASED CLOCK PLL
Maker Integrated Circuit Systems
Total Page 10 Pages
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