3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY
• Phase-Lock Loop Clock Distribution
• 10MHz to 133MHz operating frequency
• Distributes one clock input to one bank of five and one bankd
of four outputs
• Separate output enable for each output bank
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• IDT2309-1 for Standard Drive
• IDT2309-1H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Available in SOIC and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT2309 is a 16-pin version of the IDT2305. The IDT2309 accepts
one reference input, and drives two banks of four low skew clocks. The
-1H version of this device operates at up to 133MHz frequency and has
higher drive than the -1 device. All parts have on-chip PLLs which lock
to an input clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad. In the absence of an input clock, the
IDT2309 enters power down, and the outputs are tri-stated. In this mode,
the device will draw less than 25µA.
The IDT2309 is characterized for both Industrial and Commercial
NOTE: For new designs, refer to AN-233.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL
c 2002 Integrated Device Technology, Inc.