IDT23S05E buffer equivalent, 3.3v zero delay clock buffer.
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* Phase-Lock Loop Clock Distribution 10MHz to 200MHz operating frequency Distributes one cloc.
The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the r.
FUNCTIONAL BLOCK DIAGRAM
8 CLKOUT
REF
1
PLL Control Logic
3
CLK1
2
CLK2
5 7
CLK3
CLK4
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1
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