IDT79R3081E Datasheet | Integrated Device

FEATURES - Instruction set patible with IDT79R3000A, R3041, R3051, and R3071 RISC CPUs - High level of integration minimizes system cost - R3000A patible CPU - R3010A patible Floating Point Accelerator - Optional R3000A patible MMU - Large Instruction Cache - Large Data Cache - Read/Write Buffers - 43VUPS at 50MHz - 13MFlops - Flexible bus interface allows simple, low cost designs - Optional 1x or 2x clock input - 20 through 50MHz operation - "V" version operates at 3.3V - 50MHz at 1x clock input and 1/2 bus frequency only - Large on-chip caches with user configurability - 16k B Instruction Cache, 4k B Data Cache - Dynamically configurable to 8k B Instruction Cache, 8k B Data Cache - Parity protection over data and tag fields - Low cost 84-pin packaging - Superset pin- and software-patible with R3051, R3071 - Multiplexed bus interface with support for low-cost, lowspeed memory systems with a high-speed CPU - On-chip 4-deep write buffer eliminates memory write stalls - On-chip 4-deep read buffer supports burst or simple block reads - On-chip DMA arbiter - Hardware-based Cache Coherency Support - Programmable power reduction mode - Bus Interface can operate at half-processor frequency R3081 BLOCK DIAGRAM Clk In Clock Generator Unit/Clock Doubler Master Pipeline Control System Control Coprocessor (CP0) Exception/Control Registers Memory Management Registers Translation Lookaside Buffer (64 entries) Virtual Address Br Cond(3:2,0) Integer CPU Core General Registers (32 x 32) ALU Shifter Mult/Div Unit Address Adder PC Control FP Interrupt Floating Point Coprocessor (CP1) Register Unit (16 x 64) Exponent Unit Add Unit Divide Unit Multiply Unit Exception/Control Int(5:0) Physical Address Bus Data Bus Configurable Data Cache (4k B/8k B) Configurable Instruction Cache (16k B/8k B) Data...