Description
Languages
Clk2xIn
Clock Generator Unit
Master Pipeline Control System Control Coprocessor Exception/Control Registers Memory Management Registers
BrCond(3:0)
Integer CPU Core General Registers (32 x 32) ALU Shifter
Int(5:0)
Translation Lookaside Buffer (64 entries)
Mult/Div Unit Address Adder PC Control Virtual Address
32
Physical Address Bus
Instruction Cache (8kB/4kB) Data Bus Bus Interface Unit 4-deep Write Buffer 4-deep Read Buffer DMA Arbiter
Data Cache (2kB)
32
BIU Control
A
Features
- Instruction set compatible with IDT79R3000A and IDT79R3001 MIPS RISC CPUs.
- High level of integration minimizes system cost, power consumption.
- IDT79R3000A /IDT79R3001 RISC Integer CPU.
- R3051 features 4KB of Instruction Cache.
- R3052 features 8KB of Instruction Cache.
- All devices feature 2kB of Data Cache.
- “E” Versions (Extended Architecture) feature full function Memory Management Unit, including 64entry Translation Lookaside Buffer.