Description
of this processor.
The R3051, which incorporates 4kB of instruction cache and 2kB of data cache, but omits the TLB, and instead uses a simpler virtual to physical address mapping.
The R3081E, which incorporates a 16kB instruction cache, a 4kB data cache, and full function memory management unit (MMU) including 64-entry fully associative Translation Lookaside Buffer (TLB).
T
Features
- Instruction set compatible with IDT79R3000A, R3041, R3051, and R3071 RISC CPUs.
- High level of integration minimizes system cost.
- R3000A Compatible CPU.
- R3010A Compatible Floating Point Accelerator.
- Optional R3000A compatible MMU.
- Large Instruction Cache.
- Large Data Cache.
- Read/Write Buffers.
- 43VUPS at 50MHz.
- 13MFlops.
- Flexible bus interface allows simple, low cost designs.
- Optional 1x or.