ICS85411I Key Features
- Two differential LVDS outputs
- One differential CLK, nCLK clock input
- CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
- Maximum output frequency: 650MHz
- Translates any single ended input signal to LVDS levels with resistor bias on nCLK input
- Output skew: 25ps (maximum)
- Part-to-part skew: 300ps (maximum)
- Additive phase jitter, RMS: 0.05ps (typical)
- Propagation delay: 2.5ns (maximum)
- 3.3V operating supply
