900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Integrated Device Technology Electronic Components Datasheet

IDT72T4098 Datasheet

(IDT72T40xxx) 2.5 VOLT HIGH-SPEED TeraSync DDR/SDR FIFO 40-BIT CONFIGURATION

No Preview Available !

www.DataSheet4U.com
2.5 VOLT HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT CONFIGURATION
16,384 x 40, 32,768 x 40,
65,536 x 40, 131,072 x 40
IDT72T4088, IDT72T4098
IDT72T40108, IDT72T40118
FEATURES
Choose among the following memory organizations:
IDT72T4088 16,384 x 40
IDT72T4098 32,768 x 40
IDT72T40108 65,536 x 40
IDT72T40118 131,072 x 40
Up to 250MHz Operation of Clocks
- 4ns read/write cycle time, 3.2ns access time
Users selectable input port to output port data rates, 500Mb/s
Data Rate
-DDR to DDR
-DDR to SDR
-SDR to DDR
-SDR to SDR
User selectable HSTL or LVTTL I/Os
Read Enable & Read Clock Echo outputs aid high speed operation
2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
3.3V Input tolerant
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (WCS) input enables/disables Write
Operations
Read Chip Select (RCS) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of four preselected offsets
Dedicated serial clock input for serial programming of flag offsets
User selectable input and output port bus sizing
-x40 in to x40 out
-x40 in to x20 out
-x40 in to x10 out
-x20 in to x40 out
-x10 in to x40 out
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty and Full flags signal FIFO status
Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
Output enable puts data outputs into High-Impedance state
JTAG port, provided for Boundary Scan function
208 Ball Grid array (PBGA), 17mm x 17mm, 1mm pitch
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
WEN
WCLK
D0 -Dn (x40, x20, x10)
SREN SEN SCLK
WCS WSDR
INPUT REGISTER
OFFSET REGISTER
SI
SO
WRITE CONTROL
LOGIC
WRITE POINTER
RAM ARRAY
16,384 x 40,
32,768 x 40
65,536 x 40
131,072 x 40
FLAG
LOGIC
READ POINTER
FF/IR
PAF
EF/OR
PAE
FWFT
FSEL0
FSEL1
BM
IW
OW
MRS
PRS
TCK
TRST
TMS
TDO
TDI
BUS
CONFIGURATION
RESET
LOGIC
JTAG CONTROL
(BOUNDARY SCAN)
OUTPUT REGISTER
READ
CONTROL
LOGIC
Vref
HSTL
HSTL I/0
CONTROL
OE
Q0 -Qn (x40, x20, x10)
EREN
ERCLK
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
RT
MARK
RSDR
RCLK
REN
RCS
5995 drw01
DECEMBER 2003
DSC-5995/8


Integrated Device Technology Electronic Components Datasheet

IDT72T4098 Datasheet

(IDT72T40xxx) 2.5 VOLT HIGH-SPEED TeraSync DDR/SDR FIFO 40-BIT CONFIGURATION

No Preview Available !

IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
PIN CONFIGURATIONS
A1 BALL PAD CORNER
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
A
VCC VCC D38 D1 D4
D7 D9 GND GND Q1 Q3
Q5 Q7 Q9 VDDQ VDDQ
B
D35 D36 D39 D2
D5 D8 HSTL GND GND Q0 Q2 Q4 Q6 Q8 Q22 Q23
C
D34 D37
D0
D3
D6 VCC VCC GND GND VDDQ VDDQ VDDQ VDDQ Q20 Q21 Q24
D
D33 D32 D31 VCC VCC VCC VCC GND GND VDDQ VDDQ VDDQ VDDQ Q27 Q26 Q25
E
D30 TDI TRST GND
VDDQ MARK Q29 Q28
F
TCK TMS TDO VDDQ
VDDQ RCS
RT
REN
G
WCLK FWFT PAF VDDQ
GND GND GND GND
GND VDDQ OE RCLK
H
WEN WCS FF/IR VDDQ
GND GND GND GND
GND VDDQ SCLK
SI
J
MRS FSEL1 FSEL0 GND
GND GND GND GND
GND VDDQ SEN SREN
K
IW BM PRS VCC
GND GND GND GND
GND VDDQ SO EREN
L
WSDR RSDR OW VCC
GND VDDQ PAE ERCLK
M
D27 D28 D29 VCC
VDDQ EF/OR Q30 Q31
N
D23 D20 D26 VCC VCC VCC VCC GND GND VDDQ VDDQ VDDQ VDDQ Q32 Q33 Q34
P
D24 D21 D18 GND VCC VCC VCC GND GND VDDQ VDDQ VDDQ VDDQ Q35 Q36 Q37
R
D25 D22 D19 D16 D14 D12 D10 GND GND Q19 Q17 Q15 Q13 Q11 Q38 Q39
T
VCC VCC VREF D17 D15 D13 D11 GND GND Q18 Q16 Q14 Q12 Q10 VDDQ VDDQ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
5995 drw02
PBGA: 1mm pitch, 17mm x 17mm (BB208-1, order code: BB)
TOP VIEW
2


Part Number IDT72T4098
Description (IDT72T40xxx) 2.5 VOLT HIGH-SPEED TeraSync DDR/SDR FIFO 40-BIT CONFIGURATION
Maker Integrated Device Technology
Total Page 30 Pages
PDF Download

IDT72T4098 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 IDT72T4098 (IDT72T40xxx) 2.5 VOLT HIGH-SPEED TeraSync DDR/SDR FIFO 40-BIT CONFIGURATION
Integrated Device Technology





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy