Datasheet Details
| Part number | IDTCSPT857A |
|---|---|
| Manufacturer | Integrated Device Technology |
| File Size | 163.55 KB |
| Description | 2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| Download | IDTCSPT857A Download (PDF) |
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Download the IDTCSPT857A datasheet PDF. This datasheet also includes the IDTCSPT857 variant, as both parts are published together in a single manufacturer document.
| Part number | IDTCSPT857A |
|---|---|
| Manufacturer | Integrated Device Technology |
| File Size | 163.55 KB |
| Description | 2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| Download | IDTCSPT857A Download (PDF) |
|
|
|
: IDTCSPT857/A • Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications • Operating frequency: 60MHz to 200MHz • Standard speed: PC1600 (DDR200), PC2100 (DDR266) • A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333) • 1 to 10 differential clock distribution • Very low skew (<100ps) • Very low jitter (<75ps) • 2.5V AVDD and 2.5V VDDQ • CMOS control signal input • Test mode enables buffers while disabling PLL • Low current power-down mode • Tolerant of Spread Spectrum input clock • Available in 48-pin TSSOP and 56-pin VFBGA packages The CSPT857 is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT).
External feedback pins (FBIN, FBIN) for synchronization of the outputs to the input reference is provided.
A CMOS Enable/Disable pin is available for low power disable.
www.DataSheet4U.com IDTCSPT857/A 2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 2.
| Part Number | Description |
|---|---|
| IDTCSPT857 | 2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
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