Datasheet Details
| Part number | IDTCSPT857D |
|---|---|
| Manufacturer | Integrated Device Technology |
| File Size | 180.14 KB |
| Description | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| Download | IDTCSPT857D Download (PDF) |
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| Part number | IDTCSPT857D |
|---|---|
| Manufacturer | Integrated Device Technology |
| File Size | 180.14 KB |
| Description | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| Download | IDTCSPT857D Download (PDF) |
|
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: IDTCSPT857D • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications requiring improved output crosspoint voltage • Operating frequency: 60MHz to 220MHz • Very low skew: – <100ps for PC1600 - PC2700 – <75ps for PC3200 • Very low jitter: – <75ps for PC1600 - PC2700 – <50ps for PC3200 • 2.5V AVDD and 2.5V VDDQ for PC1600-PC2700 • 2.6V AVDD and 2.6V VDDQ for PC3200 • CMOS control signal input • Test mode enables buffers while disabling PLL • Low current power-down mode • Tolerant of Spread Spectrum input clock • Available in 48-pin TSSOP and TVSOP, 40-pin VFQFPN, and 56pin VFBGA packages The CSPT857D is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT).
External feedback pins (FBIN, FBIN) for synchronization of the outputs to the input reference is provided.
A CMOS Enable/Disable pin is available for low power disable.
www.DataSheet4U.com IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 2.5V - 2.
| Part Number | Description |
|---|---|
| IDTCSPT857 | 2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
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| IDTCSPT857C | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
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