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IS42S16400 - SYNCHRONOUS DYNAMIC RAM

Description

A0-A11 BA0, BA1 I/O0 to I/O15 CLK CKE CS RAS CAS Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE LDQM UDQM Vcc GND Vcc Q GNDQ NC Write Enable Lower Bye, Input/Output Mask Upper Bye, Input/Output Mask

Features

  • Clock frequency: 166, 133, 100 MHz.
  • Fully synchronous; all signals referenced to a positive clock edge.
  • Internal bank for hiding row access/precharge.
  • Single 3.3V power supply.
  • LVTTL interface.
  • Programmable burst length.
  • (1, 2, 4, 8, full page).
  • Programmable burst sequence: Sequential/Interleave.
  • Self refresh modes.
  • 4096 refresh cycles every 64 ms.
  • Random column address every clock cycle.

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Full PDF Text Transcription

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www.DataSheet4U.com IS42S16400 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 166, 133, 100 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single 3.
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