state bus sram.
DESCRIPTION
* 100 percent bus utilization
* No wait cycles between Read and Write
* Internal self-timed write cycle
* Individual Byte Write Control
.
They are organized as 256K words by 72 bits, 512K words
by 36 bits and 1M words by 18 bits, fabricated with ISSI's
adv.
* 100 percent bus utilization
* No wait cycles between Read and Write
* Internal self-timed write cycle
* Individual Byte Write Control
* Single Read/Write control pin
* Clock controlled, registered address,
data and control .
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