28F128P33
Overview
- Architecture: - Multi-Level Cell Technology: Highest Density at Lowest Cost - Asymmetrically-blocked architecture - Four 32-KByte parameter blocks: top or bottom configuration - 128-KByte main blocks
- Voltage and Power: - VCC (core) voltage: 2.3 V - 3.6 V - VCCQ (I/O) voltage: 2.3 V - 3.6 V - Standby current: 70 µA (Typ) for 256-Mbit - 4-Word synchronous read current: 16 mA (Typ) at 52MHz
- Quality and Reliability - Operating temperature: -40 °C to +85 °C - Minimum 100,000 erase cycles per block - ETOX™ VIII process technology (130 nm)
- Security: - One-Time Programmable Registers: - 64 unique factory device identifier bits - 64 user-programmable OTP bits - Additional 2048 user-programmable OTP bits - Selectable OTP space in Main Array: - Four pre-defined 128-KByte blocks (top or bottom configuration. - Entire Array OTP (Top or Bottom Config.) - Absolute write protection: VPP = VSS - Power-transition erase/program lockout - Individual zero-latency block locking - Individual block lock-down
- Software: - 20 µs (Typ) program suspend - 20 µs (Typ) erase suspend - Intel® Flash Data Integrator optimized - Basic Command Set and Extended Command Set compatible - Common Flash Interface capable
- Density and Packaging - 56-Lead TSOP package (64, 128, 256, 512Mbit) - 64-Ball Intel® Easy BGA package (64, 128, 256, 512-Mbit) - Intel® QUAD+ SCSP (64, 128, 256, 512-Mbit) - 16-bit wide data bus
- P33 is the latest generation of Intel StrataFlash® memory devices. Offered in
