28F128P30
Key Features
- High performance
- Security - 85/88 ns initial access - One-Time Programmable Registers:
- 64 unique factory device identifier bits - 40 MHz with zero wait states, 20 ns clock-to
- 64 user-programmable OTP bits data output synchronous-burst read mode
- Additional 2048 user-programmable OTP bits - 25 ns asynchronous-page read mode - Selectable OTP Space in Main Array: - 4-, 8-, 16-, and continuous-word burst mode
- 4x32KB parameter blocks + 3x128KB main - Buffered Enhanced Factory Programming blocks (top or bottom configuration) (BEFP) at 5 µs/byte (Typ) - Absolute write protection: VPP = VSS - 1.8 V buffered programming at 7 µs/byte (Typ) - Power-transition erase/program lockout
- Architecture - Individual zero-latency block locking - Multi-Level Cell Technology: Highest Density - Individual block lock-down at Lowest Cost
- Software - Asymmetrically-blocked architecture - 20 µs (Typ) program suspend - Four 32-KByte parameter blocks: top or - 20 µs (Typ) erase suspend bottom configuration - Intel® Flash Data Integrator optimized - 128-KByte main blocks - Basic Command Set and Extended Command
- Voltage and Power Set compatible - VCC (core) voltage: 1.7 V - 2.0 V - Common Flash Interface capable - VCCQ (I/O) voltage: 1.7 V - 3.6 V
- Density and Packaging - Standby current: 55 µA (Typ) for 256-Mbit - 64/128/256-Mbit densities in 56-Lead TSOP - 4-Word synchronous read current: package 13 mA (Typ) at 40 MHz - 64/128/256/512-Mbit densities in 64-Ball
