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J113A Datasheet Preview

J113A Datasheet

N-Channel JFET

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J111-2-3A
J111/A, J112/A, J113/A N-Channel JFET
Features
InterFET N0132S Geometry
Low Noise: 1.2 nV/√Hz Typical
High Gain: 15mS Typical
RoHS Compliant
SMT, TH, and Bare Die Package options.
Applications
Choppers
Commutators
Analog Switches
Description
The -25V InterFET J111/A, J112/A, and J113/A
JFET’s are targeted for high gain low noise
switching, commutator, and chopper applications.
Source 1
Drain 2
Gate 3
Drain 2
Source 1
SOT23 Top View
3 Gate
TO-92 Bottom View
Product Summary
Parameters
BVGSS Gate to Source Breakdown Voltage
IDSS
Drain to Source Saturation Current
VGS(off) Gate to Source Cutoff Voltage
J111/A Min
J112/A Min
J113/A Min
Unit
-40
-40
-40
V
-2
-2
-2
mA
-5
-2
-1
V
Ordering Information Custom Part and Binning Options Available
Part Number
Description
Case
J111; J112; J113
J111A; J112A; J113A
Through-Hole
TO-92
SMPJ111; SMPJ112; SMPJ113
SMPJ111A; SMPJ112A; SMPJ113A
Surface Mount
SOT23
SMPJ111TR; SMPJ112TR; SMPJ113TR
7“ Tape and Reel: Max 3,000 Pieces
SMPJ111ATR; SMPJ112ATR; SMPJ113ATR 13” Tape and Reel: Max 9,000 Pieces SOT23
J111COT; J112COT; J113COT
J111ACOT; J112ACOT; J113ACOT
Chip Orientated Tray (COT Waffle Pack) COT
J111CFT; J112CFT; J113CFT
J111ACFT; J112ACFT; J113ACFT
Chip Face-up Tray (CFT Waffle Pack)
CFT
Packaging
Bulk
Bulk
Minimum 1,000 Pieces
Tape and Reel
400/Waffle Pack
400/Waffle Pack
Disclaimer: It is the Buyers responsibility for designing, validating and testing the end application under all field use cases and
extreme use conditions. Guaranteeing the application meets required standards, regulatory compliance, and all safety and
security requirements is the responsibility of the Buyer. These resources are subject to change without notice.
IF35064.R00




InterFET

J113A Datasheet Preview

J113A Datasheet

N-Channel JFET

No Preview Available !

InterFET
Product
Folder
Technical
Support
Order
Now
J111-2-3A
Electrical Characteristics
Maximum Ratings (@ TA = 25°C, Unless otherwise specified)
Parameters
VRGS Reverse Gate Source and Gate Drain Voltage
IFG Continuous Forward Gate Current
PD Continuous Device Power Dissipation
P Power Derating
TJ Operating Junction Temperature
TSTG Storage Temperature
Value
-40
50
360
3.3
-55 to 125
-65 to 150
Unit
V
mA
mW
mW/°C
°C
°C
Static Characteristics (@ TA = 25°C, Unless otherwise specified, Highlighted values = A variant)
J111/A
J112/A
J113/A
Parameters
Conditions
Min Max Min Max Min Max Unit
V(BR)GSS
Gate to Source
Breakdown Voltage
VDS = 0V, IG = -1μA
-35
-40
-35
-40
-35
-40
V
IGSS
Gate to Source
Reverse Current
VGS = -15V, VDS = 0V
-1
-2
-1
-2
-1
-2
nA
VGS(OFF)
Gate to Source
Cutoff Voltage
VDS = 5V, ID = 1μA
-3 -10 -1 -5
-3
-5 -10 -2 -7 -1 -5
V
IDSS
Drain to Source
Saturation Current
VGS = 0V, VDS = 15V
20
(Pulsed)
30
5
15
2
8
mA
ID(OFF)
Drain Cutoff Current
VDS = 15V, VGS = -10V
-1
-1
-1
nA
-1
-1
-1
mA
Dynamic Characteristics (@ TA = 25°C, Unless otherwise specified, Highlighted values = A variant)
J111/A
J112/A
J113/A
Parameters
Conditions
Min Max Min Max Min Max Unit
RDS(ON)
Drain to Source
ON Resistance
VDS = 0.1V, VGS = 0V,
f = 1kHz
30
30
50
50
100
80
Ω
Cgd
Drain Gate
Capacitance
VDS = 0V, VGS = -10V,
f = 1MHz
5
5
5
pF
Cgs
Input Capacitance
VDS = 0V, VGS = -10V,
f = 1MHz
5
5
5
pF
Cgd + Cgs
Drain + Source Gate
Capacitance
VDS = VGS = 0V, f = 1MHz
28
28
28
pF
td(ON)
Turn ON Delay Time
VDD = 10V
7 (typ)
7 (typ)
7 (typ)
ns
J111/A: VGS(OFF) = -12V,
tr
Rise Time
RL = 800 Ω
6 (typ)
6 (typ)
2 (typ)
ns
J112/A: VGS(OFF) = -7V,
td(OFF)
Turn OFF Delay Time
RL = 1600 Ω
20 (typ)
20 (typ)
20 (typ)
ns
J113/A: VGS(OFF) = -5V,
tf
Fall Time
RL = 3200 Ω
15 (typ)
15 (typ)
15 (typ)
ns
J111-2-3A
Document Number: IF35064.R00
2 of 4
www.InterFET.com
InterFET Corporation
June, 2019


Part Number J113A
Description N-Channel JFET
Maker InterFET
Total Page 3 Pages
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