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International Rectifier Electronic Components Datasheet

IP2003A Datasheet

Synchronous Buck Multiphase Optimized LGA Power Block Integrated Power Semiconductors

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PD-96987A
iP2003A
Synchronous Buck
Multiphase Optimized LGA Power Block
Features:
Integrated Power Semiconductors, Drivers & Passives
• Full function multiphase building block
• Output current 40A continuous with no derating up to
TPCB = 100°C and TCASE = 100°C
• Operating frequency up to 1.0 MHz
• Proprietary packaging enables ultra low Rthj-case top
• Efficient dual sided cooling
• Small footprint low profile (9mm x11mm x 2.2mm) package
• Optimized for very low power losses
• LGA interface
• Ease of design
iP2003A Power Block
Description
The iP2003A is a fully optimized solution for high current synchronous buck multiphase applications.
Board space and design time are greatly reduced because most of the components required for each
phase of a typical discrete-based multiphase circuit are integrated into a single 9mm x 11mm x 2.2mm
power block. The only additional components required for a complete multiphase converter are a PWM
controller, the output inductors, and the input and output capacitors.
iPOWIR technology offers designers an innovative board space saving solution for applications
requiring high power densities. iPOWIR technology eases design for applications where component integration
offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for
layout, heat transfer and component selection.
Pin # Pin Name
Pin Function
1
VDD
Supply voltage for the internal circuitry.
iP2003A Internal Block Diagram
VSWS1
VSWS2
When set to logic level high, internal circuitry
of the device is enabled. When set to logic
2 ENABLE level low, the PRDY pin is forced low, the
Control and Sychronous switches are turned
off, and the supply current reduces to 10µ A.
3 PW M TTL-level input signal to M OSFET drivers.
PRDY
ENABLE
PWM
VDD
MOSFET
Driver with
dead time
control
www.irf.com
VIN
4
VSW
PGND
5, 7
6
8
9
10
10/19/05
PRDY
PGND
V SW
V IN
V SWS1
V SWS2
Power Ready - This pin indicates the status of
ENABLE or VDD. This output will be driven
low when ENABLE is logic low or when VDD
is less than 4.4V (typ.). W hen ENABLE is
logic high and VDD is greater than 4.4V (typ.),
this output is driven high. This output has a
10mA source and 1mA sink capability.
Power Ground - connection to the ground of
bulk and filter capacitors.
Switching Node - connection to the output
inductor.
Input voltage pin. External bypass ceramic
capacitors must be added directly next to the
block.
Floating pin. For internal use. Externally, short
to VSWS2 pin only.
Floating pin. For internal use. Externally, short
to VSWS1 pin only.
1


International Rectifier Electronic Components Datasheet

IP2003A Datasheet

Synchronous Buck Multiphase Optimized LGA Power Block Integrated Power Semiconductors

No Preview Available !

iP2003A All specifications @25°C (unless otherwise specified)
Absolute Maximum Ratings:
Parameter
Symbol
VIN to PGND
VDD to PGND
VIN
VDD
PWM to PGND
PWM
Enable to PGND
ENABLE
Output RMS Current
IOUT
Min
-
-
-0.3
-0.3
-
Typ Max Units
Conditions
- 16 V
- 6.0 V
- VDD +0.3 V Not to exceed 6.0V
- VDD +0.3 V Not to exceed 6.0V
- 40 A Measured at VSW
Recommended Operating Conditions:
Parameter
Symbol Min Typ Max Units
Supply Voltage
VDD
4.6 5.0 5.5
V
Input Voltage
VIN 3.0 - 13.2 V
Output Voltage
VOUT 0.8 - 3.3 V
Output Current
IOUT - - 40 A
Operating Frequency
fsw 300 - 1000 kHz
Operating Duty Cycle
D - - 85 %
Block Temperature
TBLK -40 - 125 °C
Conditions
Electrical Specifications @ VDD = 5V (unless otherwise specified):
Parameter
Symbol Min Typ Max Units
Conditions
Block Power Loss c
Turn On Delay d
Turn Off Delay d
VIN Quiescent Current
VDD Quiescent Current
PLOSS
td(on)
td(off)
IQ-VIN
IQ-VDD
-
9.4 11.7
W VIN=12V, VOUT=1.3V
-
63
-
IOUT=40A, fSW=1MHz
ns
- 26 -
L = 0.3µH
- - 1.0 mA Enable = 0V, VIN=12V
- 10 - µA Enable = 0V, VDD=5V
Under-Voltage Lockout
UVLO
Start Threshold
VSTART 4.2 4.4 4.5
V
Hysteresis
VHvs-UVLO
-
150
-
mV
Enable
ENABLE
Input Voltage High
VIH 2.1 -
-V
Input Voltage Low
Power Ready
VIL
PRDY
-
- 0.8
Logic Level High
Logic Level Low
PWM Input
VOH
VOL
PWM
4.5 4.6
-
- 0.1 0.2
V VDD=4.6V, ILoad=10mA
VDD <UVLO Threshold, ILoad = 1mA
Logic Level High
VOH 2.1 -
-V
Logic Level Low
VOL - - 0.8
 Measurement made using six 10uF (TDK C3225X5R1C106KT or equiv.) capacitors across the input (see
Fig. 8).
‚ Not associated with the rise and fall times. Does not affect Power Loss (see Fig. 9).
2 www.irf.com


Part Number IP2003A
Description Synchronous Buck Multiphase Optimized LGA Power Block Integrated Power Semiconductors
Maker International Rectifier
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IP2003A Datasheet PDF






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