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CD4021BMS Datasheet

CMOS 8-Stage Static Shift Registers

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CD4014BMS,
CD4021BMS
December 1992
CMOS 8-Stage Static Shift Registers
Features
Description
• High Voltage Types (20V Rating)
CD4014BMS -Synchronous Parallel or Serial Input/Serial Output
• Medium Speed Operation 12MHz (Typ.) Clock Rate at CD4021BMS -Asynchronous Parallel Input or Synchronous
VDD-VSS = 10V
Serial Input/Serial Output
• Fully Static Operation
• 8 Master-Slave Flip-Flops Plus Output Buffering and
Control Gating
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Full Package Temperature Range)
• 1V at VDD = 5V
• 2V at VDD = 10V
• 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
`B' Series CMOS Devices
Applications:
CD4014BMS and CD4021BMS series types are 8-stage paral-
lel- or serial-input/serial output registers having common CLOCK
and PARALLEL/SERIAL CONTROL inputs, a single SERIAL
data input, and individual parallel “JAM” inputs to each register
stage. Each register stage is a D-type, master-slave flip-flop. In
addition to an output from stage 8, “Q” outputs are also available
from stages 6 and 7. Parallel as well as serial entry is made into
the register synchronously with the positive clock line transition in
the CD4014BMS. In the CD4021BMS serial entry is synchro-
nous with the clock but parallel entry is asynchronous. In both
types, entry is controlled by the PARALLEL/SERIAL CONTROL
input. When the PARALLEL/SERIAL CONTROL input is low,
data is serially shifted into the 8-stage register synchronously
with the positive transition of the clock line. When the PARALLEL/
SERIAL CONTROL input is high, data is jammed into the 8-
stage register via the parallel input lines and synchronous with
the positive transition of the clock line. In the CD4021BMS, the
CLOCK input of the internal stage is “forced” when asynchro-
nous parallel entry is made. Register expansion using multiple
packages is permitted.
The CD4014BMS and CD4021BMS are supplied in these 16
lead outline packages:
• Parallel Input/Serial Output Data Queueing
• Parallel to Serial Data Conversion
• General Purpose Register
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H1F
H6W
Pinout
PI-8 1
Q6 2
Q8 3
PI-4 4
PI-3 5
PI-2 6
PI-1 7
VSS 8
16 VDD
15 PI-7
14 PI-6
13 PI-5
12 Q7
11 SERIAL IN
10 CLOCK
9 PARALLEL/SERIAL
CONTROL
Functional Diagram
PAR. IN
VDD
12345678
7 6 5 4 13 14 15 1 16
PARALLEL/SERIAL 9
CONTROL
11
SERIAL IN
10
CLOCK
2
Q6
12 Q7
3
Q8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-80
8
VSS
File Number 3294


Intersil Electronic Components Datasheet

CD4021BMS Datasheet

CMOS 8-Stage Static Shift Registers

No Preview Available !

Specifications CD4014BMS, CD4021BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θja
Ceramic DIP and FRIT Package . . . . . 80oC/W
θjc
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
GROUP A
SUBGROUPS TEMPERATURE
LIMITS
MIN MAX UNITS
Supply Current
IDD VDD = 20V, VIN = VDD or GND
1
+25oC
- 10 µA
2
+125oC
- 1000 µA
VDD = 18V, VIN = VDD or GND
3
-55oC
- 10 µA
Input Leakage Current
IIL VIN = VDD or GND VDD = 20
1
+25oC
-100
-
nA
2
+125oC
-1000 -
nA
VDD = 18V
3
-55oC
-100
-
nA
Input Leakage Current
IIH VIN = VDD or GND VDD = 20
1
+25oC
- 100 nA
2
+125oC
- 1000 nA
VDD = 18V
3
-55oC
- 100 nA
Output Voltage
VOL15 VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC -
50 mV
Output Voltage
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
-
V
Output Current (Sink)
IOL5 VDD = 5V, VOUT = 0.4V
1
+25oC
0.53 - mA
Output Current (Sink)
IOL10 VDD = 10V, VOUT = 0.5V
1
+25oC
1.4 - mA
Output Current (Sink)
IOL15 VDD = 15V, VOUT = 1.5V
1
+25oC
3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
1
+25oC
- -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
1
+25oC
- -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
1
+25oC
- -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25oC
- -3.5 mA
N Threshold Voltage
VNTH VDD = 10V, ISS = -10µA
1
+25oC
-2.8 -0.7 V
P Threshold Voltage
VPTH VSS = 0V, IDD = 10µA
1
+25oC
0.7 2.8
V
Functional
F VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
7
7
+25oC
+25oC
VOH > VOL < V
VDD/2 VDD/2
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Input Voltage Low
(Note 2)
VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC -
1.5 V
Input Voltage High
(Note 2)
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5
-
V
Input Voltage Low
(Note 2)
VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC -
4V
Input Voltage High
(Note 2)
VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC 11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-81


Part Number CD4021BMS
Description CMOS 8-Stage Static Shift Registers
Maker Intersil Corporation
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