HCS273MS Datasheet | Intersil

September 1995 Radiation Hardened Octal D Flip-Flop Pinouts 20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T20, LEAD FINISH C TOP VIEW MR Q0 D0 D1 Q1 Q2 D2 D3 1 2 3 4 5 6 7 8 9 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP Features - 3 Micron Radiation Hardened CMOS SOS - Total Dose 200K RAD (Si) - SEP Effective LET No Upsets: >100 MEV-cm2/mg - Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit Day (Typ) - Dose Rate Survivability: >1 x 1012 RAD (Si)/s - Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse - Latch-Up Free Under Any Conditions - Military Temperature Range: -55o C to +125o C - Significant Power Reduction pared to LSTTL ICs - DC Operating Voltage Range: 4.5V to 5.5V - Input Logic Levels - VIL = 0.3 VCC Max - VIH = 0.7 VCC Min - Input Current Levels Ii ≤ 5µA at VOL, VOH Q3 GND 10 Description The Intersil HCS273MS is a Radiation Hardened octal D flip-flop, positive edge triggered, with reset. The HCS273MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS273MS is supplied in a 20 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND 20 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F20, LEAD FINISH C TOP VIEW 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP Ordering Information PART NUMBER HCS273DMSR HCS273KMSR HCS273D/Sample HCS273K/Sample HCS273HMSR TEMPERATURE RANGE -55o C to +125o C -55o C to +125o C +25o C +25o C +25o C SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample Sample Die PACKAGE 20 Lead SBDIP 20 Lead Ceramic Flatpack 20 Lead SBDIP 20 Lead Ceramic Flatpack Die CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation...