HCTS00MS Datasheet | Intersil

Features - 3 Micron Radiation Hardened SOS CMOS - Total Dose 200K RAD (Si) - SEP Effective LET No Upsets: >100 MEV-cm2/mg - Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) - Dose Rate Survivability: >1 x 1012 RAD (Si)/s - Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse - Cosmic Ray Upset Immunity < 2 x 10-9 Errors/Gate Day (Typ) - Latch-Up Free Under Any Conditions - Military Temperature Range: -55o C to +125o C - Significant Power Reduction pared to LSTTL ICs - DC Operating Voltage Range: 4.5V to 5.5V - LSTTL Input patibility - VIL = 0.8V Max - VIH = VCC/2 Min - CMOS Input patibility Ii ≤ 5µA at VOL, VOH 14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP3-F14 TOP VIEW A1 B1 Y1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC B4 A4 Y4 B3 A3 Y3 Description The Intersil HCTS00MS is a Radiation Hardened Quad 2-Input NAND Gate. A high on both inputs forces the output to a Low state. The HCTS00MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS00MS is supplied in a 14 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). A2 B2 Y2 GND TRUTH TABLE INPUTS An L Bn L H L H OUTPUTS Yn H H H L Ordering Information PART NUMBER HCTS00DMSR TEMPERATURE RANGE -55o C to +125o C SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample PACKAGE 14 Lead SBDIP NOTE: L = Logic Level Low, H = Logic level High HCTS00KMSR -55o C to +125o C 14 Lead Ceramic Flatpack 14 Lead SBDIP Functional Diagram An (1, 4, 9, 12) Yn HCTS00D/ Sample HCTS00K/ Sample HCTS00HMSR +25o C +25o C Sample 14 Lead Ceramic Flatpack Bn (3, 6, 8,...