HCTS160T Datasheet | Intersil

Data Sheet July 1999 File Number Radiation Hardened Synchronous Counter Intersil’s Satellite Applications Flow TM (SAF) devices are fully tested and guaranteed to 100k RAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil HCTS160T is a Radiation Hardened High Speed Presettable BCD Decade Synchronous Counter that Features an asynchronous reset and look-ahead carry logic. Counting and parallel presetting are acplished synchronously with the low-to-high transition of the clock. A low level on the synchronous parallel enable input, SPE, disables counting and allows data at the preset inputs, P0 P3, to be loaded into the counter. The counter is reset by a low on the master reset input, MR. Two count enables, PE and TE are provided for n-bit cascading. TE also controls the terminal count output, TC. The terminal count output indicates a maximum count for one clock pulse and is used to enable the next cascaded stage to count. Features - QML Class T, Per MIL-PRF-38535 - Radiation Performance - Gamma Dose (γ) 1 x 105 RAD(Si) - Latch-Up Free Under Any Conditions - SEP Effective LET No Upsets: >100 MEV-cm2/mg - Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) - 3 Micron Radiation Hardened SOS CMOS - Fanout (Over Temperature Range) - Standard Outputs 10 LSTTL Loads - Significant Power Reduction pared to LSTTL ICs - DC Operating Voltage Range: 4.5V to 5.5V - LSTTL Input patibility - VIL = 0.8V Max - VIH = VCC/2 Min - Input Current Levels Ii ≤ 5m A at VOL, VOH Pinouts HCTS160DTR (SBDIP), CDIP2-T16 TOP VIEW MR 1 CP 2 16 VCC 15 TC 14 Q0 13 Q1 12 Q2 11 Q3 10 TE 9 SPE Specifications Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical...