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ML610Q360 - 8-bit Microcontroller

Download the ML610Q360 datasheet PDF. This datasheet also covers the ML610Q359 variant, as both devices belong to the same 8-bit microcontroller family and are provided as variant models within a single manufacturer datasheet.

General Description

Equipped with a 8-bit CPU nX-U8/100, the ML610Q359 is a high-performance 8-bit CMOS microcontroller that integrates a wide variety of peripherals such as, 12-bit A/D converter, timer, synchronous serial port, UART, and voice output function.

Key Features

  • CPU.
  • 8-bit RISC CPU (CPU name: nX-U8/100).
  • Instruction system: 16-bit instructions.
  • Instruction set:Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on.
  • On-Chip debug function.
  • Minimum instruction execution time Approx 30.5 µs (at 32.768kHz system clock) Approx 0.125 µs (at 8MHz sys.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ML610Q359-LAPISSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number ML610Q360
Manufacturer LAPIS Semiconductor
File Size 703.30 KB
Description 8-bit Microcontroller
Datasheet download datasheet ML610Q360 Datasheet

Full PDF Text Transcription for ML610Q360 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for ML610Q360. For precise diagrams, tables, and layout, please refer to the original PDF.

ML610Q359/ML610Q360 8-bit Microcontroller with Voice Output Function FEDL610Q359-01 Issue Date: Jul 31, 2015 GENERAL DESCRIPTION Equipped with a 8-bit CPU nX-U8/100, the ...

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31, 2015 GENERAL DESCRIPTION Equipped with a 8-bit CPU nX-U8/100, the ML610Q359 is a high-performance 8-bit CMOS microcontroller that integrates a wide variety of peripherals such as, 12-bit A/D converter, timer, synchronous serial port, UART, and voice output function. The nX-U8/100 CPU is capable of executing instructions efficiently on a one-instruction-per-clock-pulse basis through parallel processing by the 3-stage pipelined architecture. In addition, it has an on-chip debugging function, which allows software debugging/rewriting with the LSI mounted on the board.