in-system programmable high density pld.
* HIGH-DENSITY PROGRAMMABLE LOGIC — 128 I/O Pins — 11000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machi.
for the new model. The ispLSI 3256A supports all IEEE 1149.1 mandatory instructions, which include BYPASS, EXTEST and SA.
The ispLSI 3256A is a High-Density Programmable Logic Device containing 384 Registers, 128 Universal I/O pins, five Dedicated Clock Input Pins, eight Output Routing Pools (ORP) and a Global Routing Pool (GRP) which allows complete inter-connectivity .
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