ME40P03T-G Datasheet, Matsuki

* RDS(ON)≦11mΩ@VGS=-10V
* RDS(ON)≦16mΩ@VGS=-4.5V
* Super high density cell design for extremely low RDS(ON)
* Exceptional on-resistance and maximum DC cur.

* Power Management in Note book
* DC/DC Converter
* Load Switch
* LCD Display inverter PIN CONFIGURATIO.

The ME40P03T is the P-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. FEATURES
* RDS(ON.