MAX9164 Datasheet | Maxim Integrated

Description The MAX9164 high-speed LVDS driver/receiver is designed specifically for low-power point-to-point applications. The MAX9164 operates from a single 3.3V power supply, and is pin patible with DS90LV019. The device features an independent differential driver and receiver. The MAX9164 driver output uses a current-steering configuration to generate a 3.1m A drive current. The driver accepts a single-ended input and translates it to LVDS signals at speeds up to 200Mbps over controlled-impedance media of approximately 100Ω. The transmission media may be printed circuit board traces or cables. The enable logic input, DE, is used to enable or disable the driver. The MAX9164 receiver detects a differential input as low as 100m V and translates it to single-ended output at speeds up to 200Mbps. The enable logic input, RE, is used to enable or disable the receiver. Inputs and outputs conform to the ANSI TIA/EIA-644 LVDS standard. The MAX9164 is offered in 14-lead SO and TSSOP packages, and is specified for operation from -40°C to +85°C. o 3.3V Operation o 35% Lower Power than DS90LV019 o 200Mbps Data Signaling Rate o ±1V mon-Mode Range o ±100m V Receiver Sensitivity o Flow-Through Pinout o Receiver Output High for Open Input Features Ordering Information PART MAX9164ESD MAX9164EUD TEMP RANGE -40°C to +85°C -40°C to +85°C PIN-PACKAGE 14 SO 14 TSSOP Pin Configuration TOP VIEW DE 1 DIN N.C. 2 3 14 VCC 13 N.C. 12 DO+ Applications Cell-Phone Base Stations Add/Drop Muxes Digital Cross-Connects DSLAMs Network Switches/Routers Backplane Interconnect Clock Distribution ROUT 4 N.C. 5 N.C. 6 GND 7 11 DO10 RI+ 9 8 RIRE SO/TSSOP Typical Application Circuit DIN DE ROUT RE TABLE 1. DRIVER FUNCTION TABLE INPUTS DE DIN H L (≤ 0.8V) H H (≥ 2.0V) H (> 0.8V and < 2.0V) L X X: High or low Z: High impedance OUTPUTS DO+ DOL H H L Undefined Undefined Z Z DO+ DORI+ RI100Ω 100Ω RI+ RIDO+ DO- ROUT RE DIN DE TABLE 2. RECEIVER FUNCTION TABLE INPUTS...