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MAX8550A - Intergrated DDR Power-Solution

Description

The MAX8550A integrates a synchronous-buck PWM controller to generate VDDQ, a sourcing and sinking LDO linear regulator to generate VTT, and a 10mA reference output buffer to generate VTTR.

Features

  • make the MAX8550A ideally suited for DDR memory.

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Full PDF Text Transcription

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www.DataSheet.co.kr 19-3173; Rev 0; 5/04 KIT ATION EVALU E L B A IL AVA Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards General Description The MAX8550A integrates a synchronous-buck PWM controller to generate VDDQ, a sourcing and sinking LDO linear regulator to generate VTT, and a 10mA reference output buffer to generate VTTR. The buck controller drives two external n-channel MOSFETs to generate output voltages down to 0.7V from a 2V to 28V input with output currents up to 15A. The LDO can sink or source up to 1.5A continuous and 3A peak current. Both the LDO output and the 10mA reference buffer output can be made to track the REFIN voltage.
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