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Z2V56S30BTP Datasheet 256mb Synchronous Dram

Manufacturer: Mezza

Overview: 北京亿芯伟业电子技术有限公司 电话:010-8287 3941/42/43/44 传真:010-8287 3945 http://.echip..cn 256Mb Synchronous DRAM Specification Z2V56S20BTP Z2V56S30BTP Z2V56S40BTP Deutron Electronics Corp. 8F, 68, SEC. 3, NANKING E. RD., TAIPEI 104, TAIWAN, R. O. C. TEL : 886-2-2517-7768 FAX : 886-2-2517-4575 http: // .deutron..tw 256Mb Synchronous DRAM北京亿芯伟业电子技术有限公司 电话:010-8287 3941/42/43/44 传真:010-8287 3945 http://.echip..cn 256Mb Synchronous DRAMP2V56S20BTP(4-BANKx16,777,216-WORDx4-BIT) P2V56S30BTP (4-BANK x 8,388,608-WORD x 8-BIT) P2V56S40BTP (4-BANK x 4,194,304-WORD x 16-BIT) ORDERING INFORMATION Frequency Speed(ns) Type Order Part Number Low Power Package Standard Low Power Pb-Free and Pb-Free 166MHz 6 Z2V56S20/30/40 BTP -6 400mil -6L -G6 -G6L TSOP-2 143MHz 7 Z2V56S20/30/40 BTP -7 400mil -7L -G7 -G7L TSOP-2 133MHz 7.5 Z2V56S20/30/40 BTP -75 400mil -75L -G75 -G75L TSOP-2 125MHz 8 Z2V56S20/30/40 BTP -8 400mil -8L -G8 -G8L TSOP-2 Type Designation Code Z2 V 56 S 3 0 B TP-G 7 Access Item -6 : 6ns ( 166MHz/3-3-3) -7 : 7 ns (143MHz/3-3-3) -75 : 7.5ns ( 133MHz/3-3-3) -8 : 8 ns (100MHz/2-2-2) Package Type Process Generation Function Organization Synchronous DRAM Density Interface Mezza DRAM TP : TSOP(II); G: Pb Free B : 3rd generation 0 : Random Column 2 : x4, 3 :x8, 4: x16 56 :256Mbit V :LVTTL Jan.2004 Rev.1.1 256Mb Synchronous DRAM北京亿芯伟业电子技术有限公司 电话:010-8287 3941/42/43/44 传真:010-8287 3945 http://.echip..cn 256Mb Synchronous DRAMP2V56S20BTP(4-BANKx16,777,216-WORDx4-BIT) P2V56S30BTP (4-BANK x 8,388,608-WORD x 8-BIT) P2V56S40BTP (4-BANK x 4,194,304-WORD x 16-BIT) Z2V56S20BTP (4-BANK x 16,777,216-WORD x 4-BIT) Z2V56S30BTP (4-BANK x 8,388,6084-WORD x 8-BIT) Z2V56S40BTP (4-BANK x 4,194,304-WORD x 16-BIT) PRELIMINARY Some of contents are described for general products and are subject to change without notice.

This datasheet includes multiple variants, all published together in a single manufacturer document.

General Description

Z2V56S20BTP is organized as 4-bank x 16,777,216-word x 4-bit Synchronous DRAM with LVTTL interface and Z2V56S30BTP is organized

Key Features

  • Z2V56S20BTP, Z2V56S30BTP and Z2V56S40BTP achieve very high speed clock rates up to 166MHz, and are suitable for main memories or graphic memories in computer systems. ITEM tCLK Clock Cycle Time (Min. ) CL=2 CL=3 Z2V56S20/30/40BTP -6 -7 -75 -8 - - 10 10 6 7 7.5 8 tRAS Active to Precharge Command Period (Min. ) 42 45 45 48 tRCD Row to Column Delay tAC Access Time from CLK tRC Ref /Active Command Period (Min. ) (Max. ) (Min. ) CL=2 CL=3 15 20 -- 20 6 5 5.4 5.4 60 63 67.5 20 6 6 70 V.

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