Datasheet Summary
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3.3V, 622Mbps Clock and Data Recovery
General Description
The SY69754AL is a plete Clock Recovery and Data Retiming integrated circuit for OC-12/STS-12 applications at 622Mbps NRZ. The device is ideally suited for SONET/SDH/ATM applications and other high-speed data transmission systems. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the ining data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference. The SY69754AL also includes a...