SY69952 Description
On-chip clock generation is performed by a low-jitter phase-locked loop (PLL) allowing use of 19.44MHz reference for 155.52MHz generation or a 6.48MHz reference for 51.84MHz generation. Clock recovery is performed by synchronizing the on-chip VCO directly to the ining data stream. The SY69952 meets the jitter pliance criteria of Bellcore, ITU/CCITT and ANSI standards.
SY69952 Key Features
- A plete ATM patible single chip Transmitter and Receiver
- Seamless operation with PMC-Sierra PM5345, VLSI VNS67200, IgT WAC-013-B/WAC-413-A and NEC µPD98402 UNI Processors
- Supports clock and data recovery from 51.84Mbps or 155.52Mbps NRZ or NRZI data stream
- 155.52MHz clock multiplication from 19.44MHz source or 51.84MHz clock multiplication from 6.48MHz source
- Line Receiver Inputs: No external buffering needed
- Differential output buffering
- Link Status Indication
- Loop-back testing
- 100K ECL patible I/O
- Single +5 volt power supply
SY69952 Applications
- Differential PECL Input Receive Input. These built-in line receiver inputs are