SY69754AL Description
The SY69754AL is a plete Clock Recovery and Data Retiming integrated circuit for OC-12/STS-12 applications at 622Mbps NRZ. The device is ideally suited for SONET/SDH/ATM applications and other high-speed data transmission systems. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the ining data stream.
SY69754AL Key Features
- SONET/SDH/ATM patible
- Clock and data recovery for 622Mbps NRZ data stream
- Two on-chip PLLs: one for clock generation and another for clock recovery
- Selectable reference frequencies
- Differential PECL high-speed serial I/O
- Line receiver input: no external buffering needed
- Link fault indication
- 100k ECL patible I/O
- Industrial temperature range (-40°C to +85°C)
- Available in 32-pin EPAD-TQFP