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SY87725L Key Features

  • Single 3.3V supply and 1W typ. power consumption up to 2.5Gbps. On the receive side, it includes a
  • 1.25G/625M/156Mbps up stream an integrated 4-bit serial-to-parallel data converter. On
  • 4-bit Serdes with LVDS interfaces the transmit side, it includes a synthesizer with an
  • Serial Data input sensitivity of 30mV typical integrated 4-bit parallel-to-serial data converter
  • Training mode for fast lock acquisition The SY87725L receiver has a synthesizer that
  • Link Fault Indicator (LFIN: “HIGH” = Locked) generates an internal clock from an externally supplied
  • Separate training and MUX synthesizers TTL or PECL REFCLK that can be either 155.52MHz or 77.76MHz. This internal clock
  • Loop back function for diagnostics recovery PLL if an absence of transitions on the input
  • TTL-CML Translator for MAC-to-Laser diode driver serial data stream prevents normal clock recovery. This burst control e
  • Selectable double data rate option for low cost absence of transitions on the ining serial data FPGA/ASIC MAC implementa

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SY87725L Description

Features The SY87725L is a single chip transceiver for data rates Single 3.3V supply and 1W typ. power consumption up to 2.5Gbps. On the receive side, it includes a 2.5G/1.25G/625Mbps down stream plete clock recovery and data retiming circuit with 1.25G/625M/156Mbps up stream an integrated 4-bit serial-to-parallel data converter.

SY87725L Applications

  • BPON/GPON/GEPON/EPON The serial interface for both the transmit and receive functions feature industry standard high-speed Markets differential CML I/O. The par
  • FTTH/FTTP the LVDS inputs. The first bit for the serial-to-parallel conversion can be moved using the RCV_SYNC input. The RCV_SYNC input enables the parallel wo