Datasheet4U Logo Datasheet4U.com

SY89200U - Ultra-Precision 1:8 LVDS Fanout Buffer

Description

The SY89200U is a 2.5V precision, high-speed, integrated clock divider and LVDS fanout buffer capable of handling clocks up to 1.5GHz.

Features

  • Three low-skew LVDS output banks with programmable ÷1, ÷2 and ÷4 divider options.
  • Three independently programmable output banks.
  • Guaranteed AC performance over temperature and voltage:.
  • Accepts a clock frequency up to 1.5GHz.

📥 Download Datasheet

Datasheet Details

Part number SY89200U
Manufacturer Micrel Semiconductor
File Size 500.17 KB
Description Ultra-Precision 1:8 LVDS Fanout Buffer
Datasheet download datasheet SY89200U Datasheet

📁 Similar Datasheet

  • SY89206V - DIFFERENTIAL PECL/ECL RECEIVER/BUFFER (MICREL)
  • SY89216V - DIFFERENTIAL PECL/ECL RECEIVER/BUFFER (MICREL)
  • SY89230U - Clock Divider (Micrel)
  • SY89231U - Clock Divider (Micrel)
  • SY89297U - Precision CML Dual-Channel Programmable Delay (Microchip)
  • SY89306V - 3.3V/5V 2.5GHz Differential PECL/ECL Receiver/Buffer (Microchip)
  • SY89874U - Programmable Clock Divider/Fanout Buffer (Microchip)
  • SY8002A1 - 2A Synchronous Step Down Regulator (Silergy)
  • SY8002E1 - 2A Synchronous Step Down Regulator (Silergy)
  • SY8002I - 2A Synchronous Step Down Regulator (Silergy)
Other Datasheets by Micrel Semiconductor
  • SY89202U - Precision 1:8 LVPECL Fanout Buffer
  • SY89207L - PRECISION PECL AMPLIFIER
  • SY89208V - 3GHz PECL/ECL 2:1 MULTIPLEXER
  • SY89218U - Precision 1:15 LVDS Fanout Buffer
  • SY89221U - Precision 1:15 LVPECL Fanout Buffer
  • SY89222L - 3.3V DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR
  • SY89223L - 3.3V DUAL DIFFERENTIAL LVPECL-to-LVTTL TRANSLATOR
  • SY89228U - Clock Divider

Full PDF Text Transcription

Click to expand full text
SY89200U Ultra-Precision 1:8 LVDS Fanout Buffer with Three ÷1/÷2/÷4 Clock Divider Output Banks Revision 6.0 General Description The SY89200U is a 2.5V precision, high-speed, integrated clock divider and LVDS fanout buffer capable of handling clocks up to 1.5GHz. Optimized for communications applications, the three independently controlled output banks are phase matched and can be configured for pass through (÷1), ÷2 or ÷4 divider ratios. The differential input includes Micrel’s unique, 3-pin input termination architecture that allows the user to interface to any differential signal path. The low-skew, low-jitter outputs are LVDS-compatible with extremely fast rise/fall times guaranteed to be less than 150ps.
Published: |