TP2104 Datasheet | Microchip Technology

Features - High Input Impedance and High Gain - Low-Power Drive Requirement - Ease of Paralleling - Low CISS and Fast Switching Speeds - Excellent Thermal Stability - Integral Source-Drain Diode - Free from Secondary Breakdown Applications - Logic-Level Interfaces (Ideal for TTL and CMOS) - Solid-State Relays - Analog Switches - Power Management - Telemunication Switches General Description The TP2104 low-threshold, Enhancement-mode (normally-off) transistor uses a vertical DMOS structure and a well-proven silicon-gate manufacturing process. This bination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally induced secondary breakdown. Microchip’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance and fast switching speeds are desired. Package Types 3-lead SOT-23 (Top view) DRAIN SOURCE GATE See Table 3-1 and Table 3-2 for pin information.  2020 Microchip Technology Inc. 3-lead TO-92 (Top view) SOURCE DRAIN GATE DS20005958A-page 1 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† Drain-to-Source Voltage BVDSS Drain-to-Gate Voltage BVDGS Gate-to-Source Voltage ±20V Operating Ambient Temperature, TA...