ZL30281 Datasheet | Microchip Technology

Features - 25 MHz Crystal or CMOS Input - Generates PCIe 1, 2, 3, 4, 5, 6 Jitter-pliant Clocks with CML Outputs - Four Default Configurations Selected by Hardware Pins at Reset: - Config0: 100 MHz on Output OC1 (CML) - Config1: 100 MHz on OC1, OC2 (CML) - Config2: 100 MHz on OC1 (CML), OC2 (HSTL) - Config3: 100 MHz on OC1, OC2 (CML) and 25 MHz LVCMOS on OC3 - Per-Output Controls (Using SPI or I2C Interface) - Per-Output Enable/Disable and Glitchless Start/Stop (Stop High or Low) - Precise Output Alignment Circuitry and Per Output Phase Adjustment - SPI or I2C Processor Interface - Tiny 5 mm x 5 mm VQFN Package Applications - PCIe Gen1 to Gen6 Clock Generation for PCIe Storage Systems, Riser Cards, JBOF, etc. FIGURE 0-1: Functional Block Diagram.  2022 Microchip Technology Inc. and its subsidiaries DS20006736A-page 1 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or ments regarding this publication, please contact the Marketing munications Department via E-mail at docerrors@microchip.. We wele your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://.microchip. You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and remended workarounds, may exist for current devices. As device/documentation issues bee known to us, we will publish an errata sheet. The errata will...