MT49H8M32 Key Features
- 1 Meg x 32 x 8 Banks MT49H16M16
- 2 Meg x 16 x 8 Banks
- Organization: 8 Meg x 32, 16 Meg x 16 in 8 banks
- Cyclic bank addressing for maximum data
- Non multiplexed addresses
- Non interruptible sequential burst of two (2-bit
- Up to 600 Mb/sec/pin data rate
- Programmable READ latency (RL) of 5-6
- Data valid signal (DVLD) activated as read data is
- Data mask signals (DM0/DM1) to mask first and