Datasheet4U Logo Datasheet4U.com

MT49H16M16 - 2 Meg x 16 x 8 Banks Reduced Latency DRAM

Download the MT49H16M16 datasheet PDF. This datasheet also covers the MT49H8M32 variant, as both devices belong to the same 2 meg x 16 x 8 banks reduced latency dram family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Reduced Latency DRAM (RLDRAM®) MT49H8M32.
  • 1 Meg x 32 x 8 Banks MT49H16M16.
  • 2 Meg x 16 x 8 Banks For the latest data sheet, refer to Micron’s Web site: www. micron. com/products/dram/rldram/ Features.
  • Organization: 8 Meg x 32, 16 Meg x 16 in 8 banks.
  • Cyclic bank addressing for maximum data bandwidth.
  • Non multiplexed addresses.
  • Non interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR.
  • Up to 600 Mb/sec/pi.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MT49H8M32-Micron.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
MT49H16M18 16 Meg x 18 x 8 Banks CIO RLDRAM 2 Micron Technology
MT49H16M18C SIO RLDRAM 2 Micron Technology
MT49H32M9 32 Meg x 9 x 8 Banks CIO RLDRAM 2 Micron Technology
MT49H8M36 8 Meg x 36 x 8 Banks CIO RLDRAM 2 Micron Technology
MT4903 P-Channel MOSFET MT Semiconductor

Other Datasheets by Micron Technology

Part Number Description
MT49H16M36 576Mb CIO Reduced Latency
MT49H32M18 576Mb CIO Reduced Latency
MT49H64M9 576Mb CIO Reduced Latency
MT49H8M32 1 Meg x 32 x 8 Banks Reduced Latency DRAM
MT4067-P 256K x 1 DRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM Features Reduced Latency DRAM (RLDRAM®) MT49H8M32 – 1 Meg x 32 x 8 Banks MT49H16M16 – 2 Meg x 16 x 8 Banks For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/dram/rldram/ Features • Organization: 8 Meg x 32, 16 Meg x 16 in 8 banks • Cyclic bank addressing for maximum data bandwidth • Non multiplexed addresses • Non interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR • Up to 600 Mb/sec/pin data rate • Programmable READ latency (RL) of 5-6 • Data valid signal (DVLD) activated as read data is available • Data mask signals (DM0/DM1) to mask first and • second part of write data burst • IEEE 1149.1 compliant JTAG boundary scan • 2.5V VEXT, 1.8V VDD, 1.