Datasheet Summary
128Mb: x16, x32 MOBILE SDRAM
SYNCHRONOUS DRAM
Features
- Temperature pensated Self Refresh (TCSR)
- Fully synchronous; all signals registered on positive edge of system clock
- Internal pipelined operation; column address can be changed every clock cycle
- Internal banks for hiding row access/precharge
- Programmable burst lengths: 1, 2, 4, 8, or full page
- Auto Precharge, includes CONCURRENT auto precharge, and Auto Refresh Modes
- Self Refresh Mode; standard and low power
- 64ms, 4,096-cycle refresh
- LVTTL-patible inputs and outputs
- Low voltage power supply
- Partial Array Self Refresh power-saving mode
OPTIONS MARKING LC G V
MT48G8M16LFFF, MT48G8M16LFF4, MT48LC8M16LFFF,...