MT4LC16M4G3
Description
The 16 Meg x 4 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3V to 3.6V. The MT4LC16M4H9 and MT4LC16M4G3 are functionally organized as 16,777,216 locations containing 4 bits each.
Key Features
- Single +3.3V ±0.3V power supply
- Industry-standard x4 pinout, timing, functions, and packages
- 12 row, 12 column addresses (H9) or 13 row, 11 column addresses (G3)
- High-performance CMOS silicon-gate process
- All inputs, outputs and clocks are LVTTL-compatible
- Extended Data-Out (EDO) PAGE MODE access
- Optional self refresh (S) for low-power data retention
- Plastic Packages 32-pin SOJ (400 mil) 32-pin TSOP (400 mil)
- Timing 50ns access 60ns access
- The “#” symbol indicates signal is active LOW. *Contact factory for availability Part Number Example
