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MT4LC16M4T8 - DRAM

Download the MT4LC16M4T8 datasheet PDF. This datasheet also covers the MT4LC16M4A7 variant, as both devices belong to the same dram family and are provided as variant models within a single manufacturer datasheet.

General Description

The 16 Meg x 4 DRAMs are high-speed CMOS, dynamic random-access memory devices contain-ing 67,108,864 bits organized in a x4 configuration.

The MT4LC16M4A7 and MT4LC16M4T8 are functionally organized as 16,777,216 locations containing four bits each.

Key Features

  • Single +3.3V ±0.3V power supply.
  • Industry-standard x4 pinout, timing, functions, and packages.
  • 13 row, 11 column addresses (A7) 12 row, 12 column addresses (T8).
  • High-performance CMOS silicon-gate process.
  • All inputs, outputs and clocks are LVTTL-compatible.
  • FAST-PAGE-MODE (FPM) access.
  • 4,096-cycle CAS#-BEFORE-RAS# (CBR).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MT4LC16M4A7_MicronTechnology.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
16 MEG x 4 FPM DRAM DRAM FEATURES • Single +3.3V ±0.3V power supply • Industry-standard x4 pinout, timing, functions, and packages • 13 row, 11 column addresses (A7) 12 row, 12 column addresses (T8) • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL-compatible • FAST-PAGE-MODE (FPM) access • 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms • Optional self refresh (S) for low-power data retention MT4LC16M4A7, MT4LC16M4T8 For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.