MT4LC1M16E5 Description
The 1 Meg x 16 is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x16 configuration. The 1 Meg x 16 has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#). These function like a single CAS# found on other DRAMs in that either CASL# or CASH# will generate an internal CAS#.
MT4LC1M16E5 Key Features
- JEDEC- and industry-standard x16 timing, functions, pinouts, and packages
- High-performance CMOS silicon-gate process
- Single power supply (+3.3V ±0.3V or 5V ±10%)
- All inputs, outputs and clocks are TTL-patible
- Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR), HIDDEN; optional self refresh (S)
- BYTE WRITE access cycles
- 1,024-cycle refresh (10 row, 10 column addresses)
- Extended Data-Out (EDO) PAGE MODE access
- 5V-tolerant inputs and I/Os on 3.3V devices
- Voltages 1 3.3V 5V