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MT4LC1M16E5 - EDO DRAM

General Description

The 1 Meg x 16 is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x16 configuration.

The 1 Meg x 16 has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#).

Key Features

  • JEDEC- and industry-standard x16 timing, functions, pinouts, and packages.
  • High-performance CMOS silicon-gate process.
  • Single power supply (+3.3V ±0.3V or 5V ±10%).
  • All inputs, outputs and clocks are TTL-compatible.
  • Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR), HIDDEN; optional self refresh (S).
  • BYTE WRITE access cycles.
  • 1,024-cycle refresh (10 row, 10 column addresses).
  • Extended Data-Out (EDO) PAGE MODE access.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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16Mb: 1 MEG x16 EDO DRAM EDO DRAM MT4C1M16E5 – 1 Meg x 16, 5V MT4LC1M16E5 – 1 Meg x 16, 3.3V For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/datasheets/sdramds.html FEATURES • JEDEC- and industry-standard x16 timing, functions, pinouts, and packages • High-performance CMOS silicon-gate process • Single power supply (+3.3V ±0.3V or 5V ±10%) • All inputs, outputs and clocks are TTL-compatible • Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR), HIDDEN; optional self refresh (S) • BYTE WRITE access cycles • 1,024-cycle refresh (10 row, 10 column addresses) • Extended Data-Out (EDO) PAGE MODE access • 5V-tolerant inputs and I/Os on 3.