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MT4LC16M4G3 - DRAM

General Description

The 16 Meg x 4 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3V to 3.6V.

The MT4LC16M4H9 and MT4LC16M4G3 are functionally organized as 16,777,216 locations containing 4 bits each.

Key Features

  • Single +3.3V ±0.3V power supply.
  • Industry-standard x4 pinout, timing, functions, and packages.
  • 12 row, 12 column addresses (H9) or 13 row, 11 column addresses (G3).
  • High-performance CMOS silicon-gate process.
  • All inputs, outputs and clocks are LVTTL-compatible.
  • Extended Data-Out (EDO) PAGE MODE access.
  • Optional self refresh (S) for low-power data retention.
  • 4,096-cycle CAS#-BEFORE-RAS# (CBR).

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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16 MEG x 4 EDO DRAM DRAM FEATURES • Single +3.3V ±0.3V power supply • Industry-standard x4 pinout, timing, functions, and packages • 12 row, 12 column addresses (H9) or 13 row, 11 column addresses (G3) • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL-compatible • Extended Data-Out (EDO) PAGE MODE access • Optional self refresh (S) for low-power data retention • 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms MT4LC16M4G3, MT4LC16M4H9 For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.