Sub-harmonic Receiver Integrated LNA, LO Buffer, Image Reject Mixer +2.0 dBm LO Drive Level 2.5 dB Noise Figure 15.0 dB Image Rejection 100% On-Wafer RF, DC and Noise Fig.

Chip Device Layout R1006 General Description Absolute Maximum Ratings Supply Voltage (Vd) Supply Current (Id1,Id2) .

Absolute Maximum Ratings Supply Voltage (Vd) Supply Current (Id1,Id2) Gate Bias Voltage (Vg) Input Power (RF Pin) Storage Temperature (Tstg) Operating Temperature (Ta) Channel Temperature (Tch) +4.5 VDC 180, 165 mA +0.3 VDC 0.0 dBm -65 to +165 OC -5.

XR1000

XR1001

XR1002

XR1002-BD

XR1002-QB

XR1004

XR1004-BD

XR1005

XR1005-QD

XR1006-QD

XR1007

XR1007-QD

XR1008