PDSP16116MCGGDR multiplier equivalent, 16 x 16 bit complex multiplier.
I Complex Number (16116)3(16116) Multiplication I Full 32-bit Result I 20MHz Clock Rate I Block Floating Point FFT Butterfly Support I (21)3(21) Trap I Two’s Complement F.
The PDSP16116A variant will multiply two complex (16116) bit words every 50ns and can be configured to output the compl.
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