PDSP16116 Datasheet - Zarlink Semiconductor

PDSP16116 16 by 16 Bit Complex Multiplier

16 bit input for real x data 16 bit input for imag x data 16 bit input for reaal y data 16 bit input for imag y data 16 bit output for real p data 16 bit output for img p data Clock, new data is loaded on rising edge of CLK Clock, enable X-port input register Clock, enable Y-port input register Conj.

www.DataSheet4U.com PDSP16116/A/MC 16 by 16 Bit Complex Multiplier PDSP16116/A/MC DS3858 ISSUE 3.0 June 2000 The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional two's complement. The PDSP16116/A contains four 16 x 16 Array Multipliers, two 32 bit Adder/Subtractors and all the control logic required to support Block Floating Point Arithmetic as u.

PDSP16116 Features

* s s s s s s s s s s Complex Number (16 + 16) X (16 + 16) Multiplication Full 32 bit Result 20MHz Clock Rate Block Floating Point FFT Butterfly Support -1 times -1 Trap Two's Complement Fractional Arithmetic TTL Compatible I/O Complex Conjugation 2 Cycle Fall Through 144 pin PGA or QFP packages MU

PDSP16116_ZarlinkSemiconductor.pdf