- VDD=VDDQ=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differenti.

M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit, M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit, M2S56D40ATP/ AKT is a 4-bank x 4194304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signa.

M2S56D30AKT-75

M2S56D30AKT-75AL

M2S56D30AKT-75L

M2S56D30AKT-10

M2S56D30AKT-10L

M2S56D30AKT

M2S56D30ATP

M2S56D30ATP-10

M2S56D30ATP-10L

M2S56D30ATP-75

M2S56D30ATP-75A

M2S56D30ATP-75AL

M2S56D30ATP-75L