M2V64S20/30/40DTP ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle T ime Active to Precharge Command Period Row to Column Delay Access Time from CLK Ref /Active Command Perio.

M 2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit, M 2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit, M 2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit, synchronous DRAM , with LVTTL interface. All inputs and outputs are referenced to the rising edg.

M2V64S30DTP-6

M2V64S30DTP-7

M2V64S30DTP-7L

M2V64S30DTP-8

M2V64S30DTP-8L

M2V64S30DTP

M2V64S30BTP

M2V64S30BTP-10

M2V64S30BTP-10L

M2V64S30BTP-6

M2V64S30BTP-7

M2V64S30BTP-7L

M2V64S30BTP-8