M5M4V16169DTP-7 Datasheet, Mitsubishi

PINCONFIGURATION (TOP VIEW) 1. The M5M4V16169DTP/RT is a 16M-bit Cached DRAM which integrates input registers, a 1,048,576-word by 16-bit dynamic memory array and a 1024- word by 16-bit static RAM array as a Cache memory (block size 8x16) onto a si.