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M5M4V16169DTP-7 - 16M (1M-WORD BY 16-BIT) CACHED DRAM

Download the M5M4V16169DTP-7 datasheet PDF (M5M4V16169DTP included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 16m (1m-word by 16-bit) cached dram.

Description

1.

The M5M4V16169DTP/RT is a 16M-bit Cached DRAM which integrates input registers, a 1,048,576-word by 16-bit dynamic memory array and a 1024- word by 16-bit static RAM array as a Cache memory (block size 8x16) onto a single monolithic circuit.

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Note: The manufacturer provides a single datasheet file (M5M4V16169DTP_MitsubishiElectricSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Mitsubishi
  • M5M4V16169DTP-10 - 16M (1M-WORD BY 16-BIT) CACHED DRAM
  • M5M4V16169DTP-15 - 16M (1M-WORD BY 16-BIT) CACHED DRAM
  • M5M4V16169DTP-8 - 16M (1M-WORD BY 16-BIT) CACHED DRAM
  • M5M4V16169DTP - 16M (1M-WORD BY 16-BIT) CACHED DRAM
  • M5M4V16169DRT-10 - 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
  • M5M4V16169DRT-15 - 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
  • M5M4V16169DRT-7 - 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
  • M5M4V16169DRT-8 - 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM

Full PDF Text Transcription

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MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Preliminary This document is a preliminary Target Spec. and some of the contents are subject to change without notice. DESCRIPTION PINCONFIGURATION (TOP VIEW) 1. The M5M4V16169DTP/RT is a 16M-bit Cached DRAM which integrates input registers, a 1,048,576-word by 16-bit dynamic memory array and a 1024- word by 16-bit static RAM array as a Cache memory (block size 8x16) onto a single monolithic circuit. The block data transfer between the DRAM and the data transfer buffers (RB1/RB2/WB1/WB2) is performed in one instruction cycle, a fundamental advantage over a conventional DRAM/SRAM cache.
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