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M5M5T5636UG-22 - 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

General Description

The M5M5T5636UG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit.

It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.

Key Features

  • Fully registered inputs and outputs for pipelined operation.
  • Fast clock speed: 250, 225, and 200 MHz.
  • Fast access time: 2.6, 2.8, 3.2 ns.
  • Single 2.5V -5% and +5% power supply VDD.
  • Separate VDDQ for 2.5V or 1.8V I/O.
  • Individual byte write (BWa# - BWd#) controls may be tied LOW.
  • Single Read/Write control pin (W#).
  • CKE# pin to enable clock and suspend operations.
  • Internally self-timed, registers outputs eliminate the.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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January 14, 2003 Rev.0.7 Preliminary Notice: This is not final specification. Some parametric limits are subject to change. DESCRIPTION The M5M5T5636UG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability. M5M5T5636UG operates on 2.5V power/ 1.8V I/O supply or a single 2.5V power supply and are 2.5V CMOS compatible. FEATURES • Fully registered inputs and outputs for pipelined operation • Fast clock speed: 250, 225, and 200 MHz • Fast access time: 2.6, 2.8, 3.2 ns • Single 2.5V -5% and +5% power supply VDD • Separate VDDQ for 2.5V or 1.