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M5M5T5672TG-20 Datasheet 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

Manufacturer: Mitsubishi Electric

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General Description

The M5M5T5672TG is a family of 18M bit synchronous SRAMs organized as 262144-words by 72-bit.

It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.

Renesas's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability.

Overview

Preliminary Notice: This is not final specification.

Some parametric limits are subject to change.

Key Features

  • Fully registered inputs and outputs for pipelined operation.
  • Fast clock speed: 200 MHz.
  • Fast access time: 3.2 ns.
  • Single 2.5V.
  • 5% and +5% power supply VDD.
  • Individual byte write (BWa# - BWh#) controls may be tied LOW.
  • Single Read/Write control pin (W#).
  • Snooze mode (ZZ) for power down.
  • Linear or Interleaved Burst Modes.
  • JTAG boundary scan support.

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