* complementary Q and Q output from a 4-bit latch and is available in the 16-pin packages. For higher component density applications the SN54 / 74LS77 4-bit latch is available in the 14-pin package with Q outputs omitted. CONNECTION DIAGRAMS DIP (TOP VIEW) Q0 Q1 Q1 E0
* 1 GND Q2 Q2 Q3 16 15 14 1
54LS77
Motorola
70.38 KB
4-bit d latch.
4-BIT D LATCH The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as temporary storage for binary information between processing units and in.
📁 Related Datasheet
54LS74 Dual Positive-Edge-Triggered D Flip-Flops (National Semiconductor)
54LS74A Dual D-Type Positive-Edge -Triggered Flip-Flops (Texas Instruments)
54LS75 4-BIT D LATCH (Motorola)
54LS76A DUAL J-K FLIP-FLOPS (Texas Instruments)
54LS76A DUAL JK FLIP-FLOP (Motorola)
54LS00 QUAD 2-INPUT NAND GATE (ETC)
54LS00 Quad 2-Input NAND Gates (National Semiconductor)
54LS02 Quad 2-Input NOR Gates (National Semiconductor)
54LS03 Quad 2-Input NAND Gates (National Semiconductor)
54LS04 HEX INVERTER (Motorola)
