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56F803 - 16-bit Hybrid Controller

Description

Four General Purpose Quad Timers: Timer A (sharing pins with Quad Dec0), Timers B &C without external pins and Timer D with two pins CAN 2.0 B module with 2-pin ports for transmit and receive Serial Communica

Features

  • 1.1.1.
  • Digital Signal Processing Core Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators, including extension bits 16-bit bidirectional barrel shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal a.

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Full PDF Text Transcription

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www.DataSheet4U.com Freescale Semiconductor, Inc. DSP56F803/D Rev. 13.0, 02/2004 56F803 Technical Data 56F803 16-bit Hybrid Controller • • Up to 40 MIPS at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture Hardware DO and REP loops MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes 31.5K × 16-bit words Program Flash 512 × 16-bit words Program RAM 4K × 16-bit words Data Flash 2K × 16-bit words Data RAM 2K × 16-bit words Boot Flash 6 3 3 PWM Outputs Current Sense Inputs Fault Inputs • • • • • • • • • • • Up to 64K × 16-bit words each of external Program and Data memory 6-channel PWM module Two 4-channel 12-bit ADCs Quadrature Decoder CAN 2.
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